Electronic circuits, such as integrated circuits, are used in a variety of products, from automobiles to microwaves to personal computers. Designing and fabricating these circuit devices typically involves many steps, known as a “design flow.” The particular steps of a design flow often are dependent upon the type of integrated circuit being designed, its complexity, the design team, and the integrated circuit fabricator or foundry that will manufacture the circuit. Typically, software and hardware “tools” will verify a design at various stages of the design flow by running software simulators and/or hardware emulators, and errors in the design are corrected.
Several steps are common to most design flows. Typically, the specification for the new circuit initially is described at a very abstract level as a logical design. An example of this type of abstract description is a register transfer level (RTL) description of the circuit. With this type of description, the circuit is defined in terms of both the exchange of signals between hardware registers and the logical operations that are performed on those signals. A register transfer level design typically employs a Hardware Design Language (HDL), such as the Very high speed integrated circuit Hardware Design Language (VHDL) or the Verilog language. The logic of the circuit is then analyzed, to confirm that the logic incorporated into the design will accurately perform the functions desired for the circuit. This analysis is sometimes referred to as “functional verification.”
In some instances, the functionality of the circuit design will verified by simulating the operation of the design using software. Some designs may be too large or complex to efficiently simulate using software, however. Instead, the functionality of the circuit design will verified by emulating the circuit design using a hardware emulator. Examples of hardware emulators include, for example, the VELOCE family of emulators available from Mentor Graphics Corporation of Wilsonville, Oreg., the ZEBU family of emulators available from EVE SA of Palaiseau, France, and the PALLADIUM family of emulators available from Cadence Design Systems of San Jose, Calif. An emulator typically will provide a set of primitive components for emulating the operation of a circuit design. For example, emulators, some of which may use conventional field-programmable gate array circuits, emulate the functionality of a circuit design using a combination of state elements, memories and lookup tables. Of course, other types of emulators may provide additional or alternate primitive components. For example, alternatively, an emulator may function by using combinatorial elements computing a selectable function over a fixed number of inputs.
Accordingly, before the functionality of a circuit design can be verified with an emulator, the description of the circuit design must be converted or “compiled” into a model of the design that can be implemented using the available primitive components. For example, a VHDL or Verilog description of a circuit design may be converted into a model made up of a combination of state elements, memories, lookup tables, or other primitive elements, which will implement the functionality defined in the design description. A variety of compilation algorithms are known and can be employed to compile HDL circuit design descriptions into the assortment of primitive components provided by different emulators.
Different compilation algorithms may generate different models with different characteristics, however. For example, applying a first algorithm to a portion of a circuit design may produce a model with a relatively small number of primitive components. Applying another algorithm to the same circuit portion may then alternately produce a different model with a larger number of primitive components, but having a smaller operational delay (e.g., a model that more quickly converts an input value to the appropriate output value). Moreover, various design improvement techniques can be employed to modify a model in order to enhance desirable characteristics. For example, retiming techniques may be used to alter a model so as to improve its operational speed. The retiming technique may require adding primitive components to the design, however, increasing its size. Still further, even a single compilation algorithm or design improvement technique may provide different model results depending upon the amount of processing effort applied. For example, applying a few iterations of a compilation algorithm to a circuit design may produce a model with a relatively small operational delay. Applying several more iterations of the same compilation algorithm might then produce a model with an even smaller operational delay.
The various compilation algorithms used to compile a given circuit design region into a model, design improvement techniques and corresponding processing efforts for applying those algorithms and techniques to a design, as well as other compilation variables and options are often referred to as “compilation parameters” or “compilation parameter values.” While a designer has a variety of compilation parameter values that can be used to obtain models with desired characteristics, in practice it is difficult for a designer to select an optimal combination of these compilation parameter values. Additionally, a designer typically will not employ a single combination of compilation parameter values. For example, some portions of a circuit design may have critical timing requirements, such that the emulation may not operate efficiently, or even operate correctly, if the corresponding model does not operate at a sufficiently fast speed. Other portions of the design will not have significant critical timing requirements, however. Instead, it may be more important to minimize the size of the model corresponding to these other circuit portions so that, e.g., the entire model can be emulated by a selected portion of an emulator. It therefore is undesirable to use the same combination of compilation parameter values to compile different circuit design portions with varying degrees of timing and size sensitivity.
To add to the complexity of compiling an RTL description of a circuit design into an emulator's primitive components, the design typically will be organized in a hierarchical structure. For example, a design may be made up of “modules,” with each module itself containing a description of one or more RTL circuit devices, a reference to one or more lower-level modules, or some combination of both. A module may describe the logic of a frequently-used circuit structure, such as a memory unit. With this arrangement, each occurrence of the memory unit will be represented in the design by a reference to the module, rather than with a detailed description of the circuit logic making up the memory unit. Typically, a specific combination of compilation parameter values will be used to compile a single module into a model, and the compiled model then will be used for each instantiation of the modules in the design. Some instantiations of the modules description may represent timing-critical portions of the circuit design, however, while other instantiations of the module may represent size-critical portions of the circuit design. Further, a significant feature of the circuit, such as a critical timing path, may cross a boundary of two or more modules, making it difficult to apply a single desirable combination of compilation parameter values to that circuit feature.